library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity pipemwreg is
	generic
	(
		DATA_WIDTH	: natural  :=	32;
		REG_WIDTH	: natural  :=	5
	);


	port
	(
		-- Input ports
		-- from pipeemreg
		mwreg : in std_logic;
		mm2reg : in std_logic;
		malu : in std_logic_vector(DATA_WIDTH-1 downto 0);
		mdesr : in std_logic_vector(REG_WIDTH-1 downto 0);
		-- from pipemem
		mmo : in std_logic_vector(DATA_WIDTH-1 downto 0);
		-- from outside
		cen : in std_logic;
		clk : in std_logic;
		clrn : in std_logic;

		-- Output ports
		-- to pipeid
		wwreg : out std_logic;
		-- to pipewb
		wm2reg : out std_logic;
		wmo : out std_logic_vector(DATA_WIDTH-1 downto 0);
		walu : out std_logic_vector(DATA_WIDTH-1 downto 0);
		-- to pipeid wrfnd
		wdesr : out std_logic_vector(REG_WIDTH-1 downto 0)
	);
end pipemwreg;

architecture rtl_pipemwreg of pipemwreg is
component lpm_dffe32
	PORT
	(
		aclr		: IN STD_LOGIC ;
		clock		: IN STD_LOGIC ;
		data		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
		enable		: IN STD_LOGIC ;
		q		: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
	);
end component;
component lpm_dffe5
	PORT
	(
		aclr		: IN STD_LOGIC ;
		clock		: IN STD_LOGIC ;
		data		: IN STD_LOGIC_VECTOR (4 DOWNTO 0);
		enable		: IN STD_LOGIC ;
		q		: OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
	);
end component;
component lpm_dffe1
	PORT
	(
		aclr		: IN STD_LOGIC ;
		clock		: IN STD_LOGIC ;
		data		: IN STD_LOGIC ;
		enable		: IN STD_LOGIC ;
		q		: OUT STD_LOGIC 
	);
end component;
signal aclr : std_logic;
begin
	aclr <= not clrn;
	mwwreg_r: lpm_dffe1 port map(
		aclr => aclr,
		clock => clk,
		data => mwreg,
		enable => cen,
		q => wwreg
	);
	mwm2reg_r: lpm_dffe1 port map(
		aclr => aclr,
		clock => clk,
		data => mm2reg,
		enable => cen,
		q => wm2reg
	);
	mwmo_r: lpm_dffe32 port map(
		aclr => aclr,
		clock => clk,
		data => mmo,
		enable => cen,
		q => wmo
	);
	mwalu_r: lpm_dffe32 port map(
		aclr => aclr,
		clock => clk,
		data => malu,
		enable => cen,
		q => walu
	);
	mwdesr_r: lpm_dffe5 port map(
		aclr => aclr,
		clock => clk,
		data => mdesr,
		enable => cen,
		q => wdesr
	);
end rtl_pipemwreg;
